Full-time jobs in Markham, Ontario

Find full-time jobs in Markham, Ontario and nearby towns within 25 km. Read the full details and apply.

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Within 25 km of Markham

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ASIC Design Engineer, PCIe IP Enablement
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Advanced Micro Devices, Inc

ASIC Design Engineer, PCIe IP Enablement

1 Commerce Valley Drive, Markham, ON, L3T 7X6, Canada

Full-time

Within 25 km of Markham · About 9.6 km from the city centre

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Job details

Job type: Full-time
Apply by: Oct 21, 2027
Posted: Oct 21, 2026

Original job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

We are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.

THE PERSON:

A successful candidate will have ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.

KEY RESPONSIBILITIES:

Integration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC.
Synthesis, timing, lint and cdc closure to ensure high quality design.
Responsible to implement the design related to test, debug, clocks.
Understanding of low power design techniques and have good knowledge of the UPF based power-aware flow.

Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
Drive and hands-on flow development, automation, and scripting.
Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
Technical and schedule discussion with multi-site engineers and managers

PREFERRED EXPERIENCE:

Strong understanding of Digital Design in RTL, Verilog HDL
Experience with synthesis, linting / CDC tools, equivalence checks
Knowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.
Experience with design flows, version control systems, integration and
implementation of IPs to SoC.
Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
Strong AI knowledge and experience in it's usage to develop skills and agents.
Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
Excellent problem-solving and debugging skills

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Electrical Engineering / Computer Engineering preferred

This role is not eligible for Visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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More about this job

Responsibilities

Integrate and implement AMD PCIe subsystems and deploy IP into SoCs, completing synthesis, timing, lint, CDC, test, debug, and clock-related design work. Develop and automate design flows, resolve complex technical issues, and collaborate with IP, physical design, and SoC teams across locations.

Requirements

Candidates should have substantial ASIC hardware design experience and end-to-end ownership of complex digital IP or subsystems from architecture through tape-out. Preferred qualifications include RTL and Verilog expertise, experience with synthesis and verification-quality flows, power-aware design, subsystem integration, AI-assisted development, and a bachelor's or master's degree in electrical or computer engineering.

Skills

ASIC Design
PCIe
RTL Design
Verilog HDL
IP Integration
SoC Integration
Synthesis
Lint
CDC/RDC
Equivalence Checking
Static Timing Analysis
UPF/CPF Power-Aware Design
Low-Power Design
Design Automation
Scripting
Debugging

Visa sponsorship

Not detected in the job text

Keywords

ASIC
PCI Express
PCIe
Digital Design
RTL
Verilog HDL
IP Design
IP Integration
SoC
Synthesis
Lint
CDC
RDC
LEC
STA
UPF
CPF
Power-Aware Design
Low-Power Design
DFT
DFD
Subsystem Integration
SRAM Generation
ECO
Physical Design
Tape-Out
Design Automation
Scripting
AI
Version Control

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